The inventive concept relates to a semiconductor memory device, and more particularly, to a stacked load-less static random access memory (SRAM) device in which a pair of transmission transistors is stacked on a pair of driving transistors.
Of the different types of memory devices, SRAMs offer relatively low power consumption and relatively rapid response characteristics and are widely used in cache memory devices of computers or mobile electronic products. Unit memory cells of an SRAM can be generally classified as SRAM cells that use a high resistance as a cell load device and complementary metal-oxide semiconductor (CMOS) SRAM cells that use a PMOS transistor. Unit memory cells of SRAM devices can be further classified as thin film transistor SRAM cells that use a thin film transistor as a load device and bulk CMOS SRAM cells that use a bulk transistor as a load device.
A bulk CMOS SRAM cell includes a pair of driving transistors, a pair of load transistors, and a pair of transmission transistors. The pair of driving transistors and the pair of transmission transistors consists of NMOS transistors, and the pair of load transistors consists of PMOS transistors. The bulk CMOS SRAM cell has high cell stability; however, the CMOS SRAM cell also has a low degree of integration and poor latch-up immunity with increased cell size increase since the source and drain regions of the six transistors and channel regions are arranged in a plane on a substrate.